Xilinx IP for decimation

Hi,

In my application I am acquiring samples at the rate of 1 MS/s and transmitting the data values along with the timestamp using a FPGA to RT DMA FIFO . I need to decimate the acquired sample values by a decimation factor of 15 prior to the transmission . Is there a Xilinx IP which does this, and in such cases could you please provide a link containing the documentation process for making adjustments in the settings?

Thanks.