Hello all,
I am having an issue with FPGA FIFOs. I am performing a Target-to-Host DMA transfer and I have two different configurations that use the same FIFO but have dramatically different resource allocation. In the first case shown below, the FIFO resides in a loop that will be called 1k times every time the while loop executes. In this case, when mapping the slice LUTs used are about 15%
In the second case shown below, the FIFO is called once each time the while loop executes. In this case, the estimated resource utilization with respect to slice LUTs is 107%. I guess I don't know why this behavior should be expected. Can anyone explain this to me? Thanks, Matt
