Hi
Using "SyncTime.vi" which is part of the "FPGA Timekeeper 1.1b0" library, I am keeping sync with UTC time determined by an NI-9467 GPS module. Very much like the examples. I am determining when the FPGA Timekeeper is locked to this time source using "GetStatus.vi" to monitor the "FPGA Timekeeper locked" Boolean. When set TRUE I know the time returned by "GetTime.vi" is UTC and safe to use for time-stamping.
But what I am unclear about is what happens if GPS updates stop because, say, the GPS antenna has become faulty or there is not enough satellite coverage? Will the "FPGA Timekeeper locked" Boolean go FALSE? How does it know that it is drifting and how badly it is drifting?
I really need something to indicate that the FPGA Timekeeper no longer trusts its time because updates have not been applied regularly enough or at all for a period of time. I am hoping that "FPGA Timekeeper locked" Boolean does this.
If not, is there another way, using the Timekeeper library, for me to determine if "lock" has been lost sufficiently long for time to be inaccurate?
Thanks