LabVIEW 2016 FPGA
For a newly opened VeriStand Custom FPGA project, the Communication Loop displays this.
On what do these 15 elements refer?
According to this NI-page, the DMA_READ must be only as large as the number of packets of the elements read by the FPGA.
Also, the DMA_WRITE must be only as large as the elements writen by the FPGA, right?
In the sample project, however, the DMA_READ has 15 elements and DMA_WRITE 21.
Can anyone explain this?
