Hello everyone,
I made a complicated circuit in a vi file, to ease my work, I grouped several items into several sub vi files it works normally, I tried to implement this vi file and its subs to a project to simulate the FPGA, but it gives me many errors although I put the vi file and is subs under the cRIO FPGA chosen by me.
How can I fix that?
Should unsolve the sub vi files first and upload the main file into new vi file created by the project itself and recreate the sub vi files while the project run? If yes, how can I unsolve the sub vi ?