I am using NI PXIe-1062Q Chasis (connected to a Dell workstation Precision 1700) with the following modules :
1. NI PXIe-8381
2. NI PXI 7851 R
3. NI PXIe-6738
4. NI PXIe-6535
In my workstation, I have plugged in the PCIe-8381 module for connecting NI PXIe-8381 to the computer into a PCI-E Gen 3 x16 slot. Now here are my questions :
Q.1. I am trying to control three FPGA sub-VIs from a Non-FPGA Top level VI. I have attached all the VIs. The FPGA VIs do the following:
In one FPGA VI, I switch ON a TTL signal in one DIO channel of Connector 0 of 7851R
In second FPGA VI, I set a wait time
In third FPGA VI, I switch OFF the TTL signal in that channel.
I want to generate a TTL pulse as I had posted earlier in this post which was successfully done. However, here the difference is that for all three elementary actions: switch ON, WAIT and switch OFF, I have separate VIs. When I call these VIs in sequence using FPGA references, I do not get the desired result. I set the wait time to 1 μs, so I expect to see a 1 μs TTL pulse. However, I always (even if I set WAIT time 1 second) see a 250 μs (with a jitter of 750 μs when running continuously) ON time followed by a non-linear decay on my oscilloscope. I could precisely control the timing getting a very nice TTL pulse when all three actions were in one FPGA VI (as explained in the linked post above). Now I need to separate them into three files. But it is not working as expected.
Q.2. This is related to the behaviour of different FPGA VIs. Suppose, I make two FPGA VIs: One to I switch ON a TTL signal in one DIO channel and another to I switch ON a TTL signal in any other DIO channel. If I run the VIs directly one after the other (without calling from any host) then if the first VI turn one channel ON, the second VI will turn its own channel ON but will also turn off the channel which other VI had turned ON. In fact, the contents of the second VI don't matter. Even if it's a simple WAIT VI it will turn off the channel which first VI had switched ON. This may be related to my Q.1. because I have a wait VI after Switch ON VI which might be turning off the TTL in the channel. But this work should only be done by OFF FPGA VI.
I am looking forward to suggestions.
Below are the screenshots of all VIs :
