While Loop inside a Case Structure executes only Once in FPGA Target

I`ve an NI cRIO 9012 RIO card for the HIL System. I`ve an FPGA Target file where I use a While Loop and inside a while loop I use Case Structure to check for true condition inside that i`ve the function of enabling the ports and selecting the analog and digital ports. But for my code the code is executing only once not on repeted times as we`ve in the LabVIEW Environment.

I also need help in optimizing the code. I`ve seen people using Timed While Loop in FPGA Target i`m not using in either case.:smileysurprised:

I`ve attached my FPGA file with the Version of LV2012.

Awaiting your feedback.

Thanks and Regards,

Ganesha Moorthy