Getting timing errors while implementing the interleaving using the Labview IP filter generator

Hi,

I have created a 'Multistage Multirate Filter' in Labview FPGA using 'Start IP Generator' . The following link shows the procedure

http://zone.ni.com/reference/en-XX/help/371988F-01/lvdfdtconcepts/design_fp_multirate/

When I use the interleaving technique to fill the elements in the filter for multichannel implementation . I get a timing error pertaining to the non block component on FPGA block diagram . Can you please help?

Regards