I have a NI-9148 with 4 NI-9234 RIo Cards. I seem to be having a FPGA DMA FIFO Read problem. I have a simple loop using the Invoke Node FIFO read property. My problem is that the time that the invoke read node is taking to execute is slower than the data filling up the Host DMA.
I have 16 channels of 51200 Samples/sec at 24 bits. So a rate of (51200 X 16 X 3 bytes) is 2,457,600 Bytes/sec. So, say that the FPGA collects and sends 0.1 s of data and I try to read that 0.1 seconds of data, the DMA FIFO read takes .1 seconds to execute, even with greater than .1 seconds of data already shown in the Elements remaining indicator! This effect scales with different amounts of data to be pulled from the DMA FIFO, .05, .1, .2, .3 second slices of data. it takes almost exactly that long to execute the Read DMA FIFO. .1 sec of data would be ~ 81920 elements.
On the FPGA side, I am writing to the DMA FIFO every sample available of the cRIO.