Hello,
I am trying to count the time in ticks between rising edges on two digital channels. Therefore I use a myRIO and LabVIEW 2013 SP1 on a Windows 7 PC.
As you can see in the attached picture, I use a target-scoped FIFO to pass the number of ticks between two events from SCTLs to a while-loop, where I want to send them via DMA to the RT host.
I chose this design to limit the number of DMA cannels and to increase the clock of the SCTLs (allows better precision in time). The number of ticks is determined via the built-in DSP 32bit-counter.
However, when I run the VI no data is written to the target-scoped FIFOs. "Number of Elements to write" is always 127 (128 requestet), "Number of Elements to read" is always zero. "ch0 post" indicates that the "true" state of the case structure is actually entered.
Edit: All the indicators were added for debugging purposes. The simulation on the PC indicates no errors whatsoever, but I realized that no data is written to the RT host when in actual use.
I checked out the cRIO programmers guide and the High Performace FPGA Developers Guide and fail to see where I went wrong. Yet it won't work.
I'd be happy if someone could help me fix this problem!