Hi,
I have a hybrid code (which I cannot post here but will use the attached as an example) of a VI on the FPGA target that is just a group of digital inputs. The rest of the code is on the Real-Time target. I understand there needs to be a DMA FIFO to pass information from the FPGA to the Real-Time target so the Real-Time target can share that with the host.
This is a two part question.
1. Why wouldn't the VI that's on the FPGA target be included in the block diagram of the DMA FIFO VI, say in between FPGA Write.vi and FPGA Read.vi, or some other place in the VI that passes through the digital input readings to the RT Target & Host?
2. Also, the RT-Target will need to collect the readings from the VI on the FPGA. Will I just drag in the VI that's on the FPGA into the VI on the RT-Target that's performing the control in my control system, say in a while or time loop and does the VI from the FPGA target need some conditioning in the RT system control VI?
See the note in RT Main.vi --> Timed Loop "I/O Engine"