Using SCTL in FPGA VI

Hello, guys.

We are running a FPGA VI, and for a time we were using just a While Loop.

But reading some new articles about how to improve my FPGA VI, I've seen about SCTL (Single-Cycle Time Loop).

I tried to replace the While Loop for the SCTL but when I tried to run the LabVIEW shows a message about using For Loops inside the SCTL.

In order to remove the for loops I would have to split all my build arrays and use all that coding inside the for loop as many times as for the channels I'm monitoring. Then my question is: What is more worth: using the While Loop in order to keep the For Loop or increase my code redundantly in order to use the SCTL structure?

Thank you all.

Best