Hi All,
I am working on a project making use of a cRIO 9049 and two NI 9215 modules to sample eight channels at 100 kHz. I am also using the NI 9467 module to time stamp the data measurements. The analogue input channels and the time from the timekeeper are written to two separate FIFOs. These two FIFOs are picked up in the host VI where the depth is configured and then read within a while loop.
When I set the loop timer to 10 uS I can log at 100 kHz using one 9215 module, when I add the second 9215 module at the FPGA input node, the sampling rate saturates at 90.9 kHz (whilst the loop timer is still 10 uS). I have attached images of my FPGA VI (which makes use of the timekeeper VI) and my host VI. Is my general logic in the FPGA/host VIs correct? Can anyone suggest a reason/solution for the reduction in the sampling rate when gathering data from two 9215 modules on the cRIO?
Best Regards,
Eddie
