Hi all
I am using DMA FIFO architecture to transfer 5 channel data (NI 9222 input module) from FPGA to PC host. I am using cRIO 9014 controller in my application.
I have set the size of 1024 elements on the FPGA side. FPGA loop is executing at 500 kSamples/s (i.e. every 2 us) On the host side (reading side) I am reading a big chunk of data e.g. for 17ms (No. of elements to read = 500KS/s*0.017*5(channels) = 42500).. But since this number is not exact multiple of 1024 so I defined the nearest multiple of 1024 (i.e. 43008) as the number of elements to read.. The total FIFO depth defined on the host side = 5*43008 = 215040 .
On the FPGA side the timeout is wired to "-1" so that FIFO waits indefinitely to write the data when the buffer gets full.
When I run my application I write the FIFO in a text file on the host computer. I see that everytime I run the VI I miss few data points which I thought is contributed to FIFO getting full. I tried to increase the size of FIFO on both FPGA and host side but it didn't solve the problem.
The most weired point I observed is that I am able to get continous data for the set reading size of 43008 elements and I miss exactly next 43008 elements This sequence repeats.
One of the reason I thought, might be I am reading too many elements at once and this may be slowing down the execution of the reading loop resulting in a outcome that FPGA writes faster into the FIFO than host side reads.
I changed the number of elements to read to 3072 for time = 1.23ms.. The observation was I read 3072 elements and miss next 3072 elements.It seems that the data points that I miss are not dependent on the speed of reading loop but it is somehow linked directly to the defined number of elements to read.
I am stuck at this point and unable to solve this puzzle... Any sort of help in this regard will be highly appreciated.