HI
I'm currently working on the NI PCIe-1473R Board with the XILINX VIrtex 5 LX50 FPGA chip on it. My LabVIEW version is 13.0.1 and I'm using the newest XILINX toolchain (as far as I know), PlanAhead version is:
### PlanAhead (PlanAhead) ###
****** PlanAhead v14.4 (64-bit)
**** Build 222254 by xbuild on Tue Dec 18 05:21:09 MST 2012
** Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
The problem is:
I have created a FIR-like structure (trying to parallelize the cross-correlation algorithm) using all of the 48 DSP48E slices the chip offers. This, plus some memory handling, runs in a 200MHz loop.
Up to a point in developing this program the compilation did work, taking about 10 minutes. When I now start to make little changes like adding a FIFO-DMA write (which I definately need), or an additional (if useless) multiplication, compilation time explodes, Or to be more exact, the PlanAhead step takes more than one and a half hours (I haven't had the patience to wait if it finishes at all. It doesn't exactly hang, it just works VEEERY slow!). Plus the planAhead process uses about 20GB of RAM plus about 100% of one of my CPU Cores...
I tried some other small changes, most of them compiled just fine, so I guess it must be a specific problem. I tried to compare the Xilinx Log's of a working compilation and one that doesn't. The only obvious difference during compilation (i did not compare every single line...) was, that the compiler gave a warning that now all DSP48E slices are used:
WARNING: [Designutils 20-280] Estimation has reached limit of 48 DSP slices on requested part; now using LUTs for multipliers
Is it possible that this warning slows the compiler down that much?!
This is my first post here, so please tell me if I forgot any vital information. Thanks in advance for any thoughts and help!