Hey,
I am trying to figure out a method to nicely organize my FPGA VI's parallel loops, while still having access to all of the controls and indicators. Ideally each loop would be completely contained in a subVI, but this results in not having access to the C&Is.
On Windows, you can pass in a reference to the controls and indicators and have everything work out.
Has anyone come up with a solution to this problem?
Thanks,
Tom