NI PXIe-7962R io clock for timed single cycle timed loop

Hi,

I'm developing an FPGA program on the NI PXIe-7962R and NI 5781 A/D. Using a single cycle timed loop. In the loop I read data from the A/D channels.

When selecting a clock, the performance seems to be much better when using the IO module clock rather than the on board clock, even if both are set to the same frequency. In better performance I mean less spikes in the sampled data.

1) Why is the IO module clock better? It takes more resources and so harder to get the loop to do more.

2) What is a PLL lock? In some labview examples if the host is running the FPGA, it waits for a PLL lock. What is this function? Can this effect the quality of the sampled data as well?

Thanks