I need to vent a little.
Part of my workflow will often involve queuing up a few FPGa compiles before I head home for the weekend. Especially with Vivado compiles taking so long, this is certainly preferable to sitting at my desk twiddling my thumbs for hours waiting for a bitfile.
One thing keeps snagging me though: If any RT system I an currently connected to powers off, a dialog appears that the connection tot he device has been lost. Not a problem you would think. However, the presence of this dialog prevents the compile process from completing. When I return two days later, communication with the FPGA server has been lost (due to the job being long finished and presumably scrubbed from the active jobs list).
Why is the ability to complete the FPGA compile process affected by this? Does the entire business logic for the communication with the FPGA compile server require the UI thread?