In Range and Coerce Bug/Double Limitation

December 19, 2019, 11:38 am

≫ Next: execution of two vi's one after the other.

I've run into a interesting limitation of doubles, and the "In Range and Coerce Function". I couldn't figure out for the life of me why 87.6 != 87.6. The snippet below is the vi I created to exhibit the behavior. I made sure that the upper limit and lower limit are included.

I put the following values into the controls if you want to repeat it yourself

What you will see is that 87.6 != 87.6 for the In Range and Coerce Function. I believe what is happening is with the 0.1 multiplication, the binary bits for 87.6 != the other binary bits for 87.6. So even though they appear as the same number for all intents and purposes, they are not the same number. If you change the Upper Limit to 87.7 suddenly everything works again. Or even if you change the X to 87.1 it all works as well.

It's not a bug of LabVIEW, more as a bug of binary. But I thought the community would like to see the limitations of a computer in action.

If you extend the number out to decimal points you will see that one is 87.5999999999999943 and another is 87.600000000000085

↧

execution of two vi's one after the other.

December 12, 2019, 9:23 pm

≫ Next: How to continuously write data in the text file

≪ Previous: In Range and Coerce Bug/Double Limitation

My need is to run two vi's.. (one vi followed by another)

i.e; when I run the first vi it gives certain output.

then need to enter the input to second vi from the output of first vi and when second vi runs automatically it should provide final output.

is this operation is possible

please help me...........

Thanks....

↧

How to continuously write data in the text file

December 12, 2019, 8:49 pm

≫ Next: Cluster Bundle/Unbundle Best Practice?

≪ Previous: execution of two vi's one after the other.

Hi everyone,

I am trying to write continuous data in the text file but it only write to the current value can anyone guide me what should i need to do for writing the data the continuous data. Please refer to the attached file.

Thanks in advance.

Regards,

Taufeey

↧

Cluster Bundle/Unbundle Best Practice?

December 19, 2019, 8:31 pm

≫ Next: Windows7 から Windows10 へアップデートすると、エラーコード -604 が発生

≪ Previous: How to continuously write data in the text file

I’m wondering if there is a best practice concerning the Bundle/Unbundle by Name for nested clusters. For the action, I have the two example below I’m thinking about for both the Unbundle (left) and the Bundle (right). Most of the time, I have gone with the visually simple lower methods, just using a single node to perform the action.

I’ve seen others go with the top version.

In benchmarking both versions, there doesn’t seem to be much a difference in the unbundle operation, but almost a twice the time in the Bundle operation, which may make sense with all the memory copies being made.

But something recently happening to me to make me wonder if breaking the unbundle into cluster level sections make sense. I added a copy of a subcluster (original named DataB) to the larger Orange cluster. Named the new one DataA, and made it the first control (0) in the Orange cluster. I found that in a few unbundle by name functions I already had in the code with “Orange.DataB.Numeric” LabVIEW had gone and changed them to “Orange.DataA.Numeric”. The new subcluster’s name. I found when errors popped up in parts of the code that I did not think I had touched. And changed them back to “Orange.DataB.Numeric”.

I don’t remember seeing that happen in 20 years. But I’m wondering if making the best practice of an unbundle operation the one where I do it in steps. I think it might prevent LabVIEW from changing the code again in the situation I had. I’ll stick with the single Bundle operation because it takes too large a relative time hit.

What do people think?

↧

Windows7 から Windows10 へアップデートすると、エラーコード -604 が発生

December 19, 2019, 8:45 pm

≫ Next: Direction Finding ON USRP X310

≪ Previous: Cluster Bundle/Unbundle Best Practice?

Moved to Japanese board. It's under Regional Communities.

↧

Direction Finding ON USRP X310

December 19, 2019, 11:08 pm

≫ Next: Variant to data with visa ressource

≪ Previous: Windows7 から Windows10 へアップデートすると、エラーコード -604 が発生

Hi All. i am working on frequency peak detection. Can anyone guide me is there any method to detect phase angle of peak frequency in USRP X310 (1 TX, 2 RX). For example attached is my RX vi, Whether i am able to detect the angle from which that peak is coming??

Thanks and regards

↧

Variant to data with visa ressource

December 20, 2019, 12:08 am

≫ Next: USRP receiver

≪ Previous: Direction Finding ON USRP X310

Hey!

I am just going trough the "continuous measurement and logging" example with QMH - step by step on one monitor and rebuilding it on the other monitor.

At the moment I am struggeling with the "variant to data" function.

What I try to do here is (just a snip-it), that I have an UI queue for all my settings and all the general things I need to care about. For every instrument I want to use I do extra while loops. Finally followed by a logging queue or anything like that.

For references to my visa instruments I want to use a type def (cluster -> visa session) and hand it over to the other loop by a message into the desired loop. Here I use "variant to data" to translate the message based on my type definition and add it to my shift register loop for hardware reference (as it is also done in the code example).

I added the "variant to serial data" function to see what he translated.

"UI Typedef" is the information of the reference in the UI loop.

"Erfassung Typedef" should be the same as "UI Typedef" if it's working.

"Nachrichtendaten" is the message in send over to the instrument loop (and it shows the data I need USB0...).

"Daten-String" is the information out of the "variant to serial data" function and shows maybe the problem. There is a " &" added in front of the adress and I don't know why.

Maybe you can help me. Anyway I want to wish you a merry merry xmas (peaceful and blessed!).

Greetings,

Fabian

↧

USRP receiver

December 20, 2019, 3:37 am

≫ Next: Direction Finding ON USRP X310

≪ Previous: Variant to data with visa ressource

Moved to USRP board

↧

Direction Finding ON USRP X310

December 19, 2019, 11:08 pm

≫ Next: Error -197362020 When Reading Tags from SystemLink Server

≪ Previous: USRP receiver

Moved to USRP board

↧

Error -197362020 When Reading Tags from SystemLink Server

December 20, 2019, 6:22 am

≫ Next: 3 ThermoCouples With MyDAQ University kit

≪ Previous: Direction Finding ON USRP X310

Hello All,

I am experiencing an interesting issue that I cannot seem to get a hold on.
This system includes an NXG 4.0 Program and a SystemLink Server (with OPC UA).

Utilizing the OPC UA, I am creating monitors (tags) that I can read in my NXG Program.
I am able to read the tags but before they are read I continue to get an Error -197362020 (I will attach a photo to this post of the actual error).

This is odd to me because it is still reading the data and displaying it in the Indicators I have made for the particular tag I want to read. But it gives me the errors every time the program is ran.

Any ideas here?

↧

3 ThermoCouples With MyDAQ University kit

December 20, 2019, 11:51 am

≫ Next: intersection on XY graph

≪ Previous: Error -197362020 When Reading Tags from SystemLink Server

Hello I am wondering if it is possible to use 3 thermocouples on a MyDAQ. Can I use the AIO and AO spots for all three thermocouples?

↧

intersection on XY graph

December 20, 2019, 2:44 pm

≫ Next: Arbitrary Waveform Generator with Script Output Mode - Need to Display a Marker with a Trigger While Switching Between Waveforms

≪ Previous: 3 ThermoCouples With MyDAQ University kit

Hi,

how to find intersection on graph entering two points???

↧

Arbitrary Waveform Generator with Script Output Mode - Need to Display a Marker with a Trigger While Switching Between Waveforms

December 20, 2019, 3:14 pm

≫ Next: Basys 2 FPGA board

≪ Previous: intersection on XY graph

Hi, I am currently using NI PXIe-5450. Output mode is configured to script. I've created two waveforms that are downloaded to AWGs memory. I've configured a script digital edge (rising edge) trigger with an external source (into PFI0) and use the following script.

Using a function generator set to a pulse hooked up to PFI1, when I press trigger, my waveform changes from waveform 1 to waveform 2. Pressing again, it changes from 2 to 1. My program and setup works just as I needed it to. I now need to generate a marker every time a hardware trigger is received but I am having a hard time with the syntax. I browsed some NI Fgen Signal Generator Help like Common Scripting Use Cases and Scripting Instructions which helped but I wanted to see if anyone could help brainstorming or has any ideas/solutions. With the script below:

you get a marker every time the waveform is repeated while waiting for the trigger, we only need one marker when the script trigger is received. We've been able to sort of cheat by only adding this marker to the second waveform (below), this way we can distinguish with a marker exactly when we switch to the second waveform and thus when the hardware trigger was received.

I'd like for this script to achieve something like:

- generate waveform 1 until trigger is received

- once trigger is received, generate waveform 2 with a marker at the beginning and then continue generating waveform 2 without a marker.

- once trigger is received, generate waveform 1 with a market at the beginning and then continue generating waveform 1 without a marker and repeat

I've tried a few things that didn't work. I've been looking through the scripting instructions, like repeat/end repeat etc. to try things, but usually my ideas don't work due to a syntax error.

(Example: I tried generating a marker using repeat once, generate marker. This is an issue because you can't only generate a marker. A marker must be generated with a waveform).

Let me know if you have any ideas! Thanks.

↧

Basys 2 FPGA board

December 12, 2019, 11:47 pm

≫ Next: ERROR: [Synth 8-5809] in FPGA Complation

≪ Previous: Arbitrary Waveform Generator with Script Output Mode - Need to Display a Marker with a Trigger While Switching Between Waveforms

Hello.I have basys 2 fpga board but I can not communicate to program this board.And I cant not is in the target and devices section.If you know the reason please help.

↧

ERROR: [Synth 8-5809] in FPGA Complation

December 13, 2019, 12:51 am

≫ Next: Inserting/deleting rows in table

≪ Previous: Basys 2 FPGA board

Hello:

When i'm using FlexRIO with Cameralink 1483, I got a xilinx compile error says Error 8-5809.

I can successly compile some simpler VI in the same project, and the failed one is only using more resource, more logic, no odd things like CLIP or XIP has been added.

And the log says there are problem in interface.vhd, I checked this file and it a file comes with LabVIEW FPGA, encrypted, can't say there is anything wrong with that.

I compared the Interface.vhd of a working VI, the difference is working VI get me a Interface.vhd of bytes = 28752, and the one with error have a Interface.vhd bytes = 38240? Is this the reason my VI fail to compile? I did add 5 FIFOs in VI-scope to add some function, Also I added 4 FIFO to host (which should be fine since FlexRIO Controller should have 16 or maybe more DMA channel).

Can anyone give me some advice? Thanks!

Here is the compile result:

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:445]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:446]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:447]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:448]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 385.238 ; gain = 154.605
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace {C:/NIFPGA/jobs/K0WSe4L_wgI55K2/.Xil/Vivado-22556-Laptop-G7/realtime\SmallBlockTop.tcl}"
invoked from within
"synth_design -keep_equivalent_registers -top "SmallBlockTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl" line 31)
invoked from within
"source "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 15:28:43 2019...

Compilation Time
---------------------------
Date submitted: 12/13/2019 3:27 PM
Date results were retrieved: 12/13/2019 3:28 PM
Time waiting in queue: 00:08
Time compiling: 01:05
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 00:56

-------------------------------------------------------------------------------------------------------

and there is the Xilinx log:

WARNING: Default location for XILINX_VIVADO_HLS not found:

WARNING: [Common 17-306] Update version (2017.2.1_AR70173) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR70069) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR69663) does not match product version (2017.2.1).

****** Vivado v2017.2.1_AR71289_AR70173_AR70069_AR69663_AR69485 (64-bit)

**** SW Build 1957588 on Wed Aug 9 16:32:24 MDT 2017

**** IP Build 1948039 on Wed Aug 9 18:19:28 MDT 2017

INFO: [Common 17-1460] Use of init.tcl in C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl is deprecated. Please use Vivado_init.tcl

Sourcing tcl script 'C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl'

# package require struct::list

# package require struct::set

# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 1000000;"

# ::struct::set add vhd_files [glob *.\[vV\]\[hH\]\[dD\]]

# ::struct::set subtract vhd_files {"BuiltinFIFOCoreFPGAwFIFOn0.vhd" "BuiltinFIFOCoreFPGAwFIFOn1.vhd" "BuiltinFIFOCoreFPGAwFIFOn11.vhd" "BuiltinFIFOCoreFPGAwFIFOn5.vhd" "BuiltinFIFOCoreFPGAwFIFOn6.vhd" "BuiltinFIFOCoreFPGAwFIFOn9.vhd"}

# read_vhdl $vhd_files

# if {[llength [glob -nocomplain *.\[xX\]\[dD\]\[cC\]]] > 0} {

# set CoreXDCFilesFH [open CoreXDCList.txt r]

# set xdc_files_xci [split [read $CoreXDCFilesFH] "\n"]

# close $CoreXDCFilesFH

# set xdc_files_all [glob *.\[xX\]\[dD\]\[cC\]]

# set xdc_files_source [::struct::set difference $xdc_files_all $xdc_files_xci]

# set xdc_files [read_xdc $xdc_files_source]

# foreach xdc_file $xdc_files_xci {

# if {[file exists $xdc_file]} {

# lappend xdc_files [read_xdc -ref [file rootname $xdc_file] $xdc_file]

# }

# set_property PROCESSING_ORDER {LATE} [get_files $xdc_files]

# }

# read_edif [glob *.\[eE\]\[dD\]\[fFnN\]]

# read_edif [glob *.\[eE\]\[dD\]\[iI\]\[fF\]]

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn0.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn0.dcp