I want to use an occurrence to stop a SCTL on FPGA based on another loop stopping.
These are both inside a standard While loop (the same loop, in a case structure).
Simulation seems to show a problem similar to that described on a standard desktop VI - the "Generate Occurrence" node creates a single reference regardless of how many times it is called, and then if I set Ignore Previous to "False" I get previous iterations' "Set Occurrence" triggering it, even if I have previously Waited on that occurrence (of the Occurrence).
Is there a good workaround for this?
I can try setting Ignore Previous to True, but then I suspect there exists some potential for timing problems. I don't know if using FPGA provides some improvement here, but I wouldn't bet on it not being a potential "race-like" condition.
A rough outline of the desired VI is below:
![Example_VI_BD.png Example_VI_BD.png]()
Some possible alternatives include a boolean Register or a Local Variable boolean indicator or control, or (more expensively, I think) some sort of VI-scoped FIFO (guess the register is a much better plan).
Can I use Occurrences here? Are they a good tool (and if not, when are they a good tool? Only when timeout != 0 and ignore previous is true?)