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What does "Locked" status really mean in FPGA Timekeeper

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The help says, "FPGA Timekeeper locked is TRUE if the FPGA Timekeeper has locked on to and is tracking the given time reference."

 

That's not very specific. 

 

- The Timekeeper is only "tracking the given time reference" when "Sync Time.vi" is called by the code, right?  Otherwise isn't it just predicting time base on the FPGA clock cycle, and apparently some filtering, gain and interpolation?  That wouldn't really be tracking the time reference.

 

- Is the Timekeeper checking the interval at which Sync Time.vi is called?

- Is it comparing the offset of the two time values input to Sync Time.vi  to its internal prediction?

- Is it making some judgement after a series of Sync Time.vi calls (how many?) that it has figured out the relative variations between the time reference and the FPGA clock?  How does it make that judgement?

- If a long time passes between Sync Time.vi calls does it decide it has lost its lock?

- Does calling Time Synce too frequently or too infrequently contribute to not achieving locked status, or to losing it?

 

Thanks for the help!  I love the idea of the FPGA Timekeeper but I don't know how to interpret the lock.  I can get the offset from the time reference, but what I'd really love to know is the size of the error when calling Time Synce.vi.


Hitachi F-1080 25-pin serial connection data aquisition

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Hello, I have a flourescence detector (Hitachi F-1080) that I am trying to aquire a signal from with using labview. I currently have labview 2014 and some programming already in place to control my valves, method timings, and pump. My detector was originally connected through recorder port (from the back of the F-1080) via coaxial to a box that communicates with my PC. This shows a weak signal in the form of millivolts. I have since then changed to the 25-pin port that is a digital signal. I am trying to create a VI that will aquire the signal and display a chromatograph. It is connected thru COM1 right now but am unable to aquire any kind of signal at the moment. 

 

Megan

Error -229771 at DAQmx Start Task.vi

String to Binary

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Hello, im new in labview and i have a problem.

 

I have an Input String and i need a binary exit.

For example: if i write at the input HELLO WORD the result is: 01001000010001010100110001001100010011110010000001010111010011110101001001000100

 

And viceversa, if i have in the input 01001000010001010100110001001100010011110010000001010111010011110101001001000100 the result must be: HELLO WORD

 

 

Please let me know if any more info is needed, thank you for the help!

Convert LabVIEW 5.0.1 to LabVIEW 2012

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Hello Guys,

 

Good Day!

 

Please help me to convert some series of VI's (sorry not in LLB) from 5.0.1 to 2012.

 

Thank you very much in advanced! Cheers! :smileywink:

 

 

Best Regards,

 

Dennis

Running multiple commands in command prompt

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Hi
I am having the following scenario
open command prompt
open xilinx command prompt
switch to xmd console
run a set of commands
print the final output to screen


I am having the following doubts


Can system exec.vi take multiple commands as standard input?

If yes what is the delimiter?
If no what other options I have to achieve my goal

Thanks

FFT in FPGA

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Hi, 

 

the following is the snpshopt of the BD to do an FFT on an Analog input. A sinusoidal input is given to the NI-9215 via a signal generator. The FFT ouput observed does not match with the frequency of the signal generator. Should the code be changed??. Im using an cRIO 9022 with a NI-9114 target.

 

The transform length in the FFT block=512.

 

Rgds'

Raster scan

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Hii All,

I am very new to labview. I have a PCI card DAQ I want to use for data acquisition for my home-made AFM. I need a raster scan generation for the x-y axis and a z-feedback  signal output. Any ideas guys?

 

Kind Regards,

Opuk


FFT of Sine Wave-FPGA

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Also tried generating a sine wave of 50 Hz and an amplitude of 100 and then do an FFT. But the FFT does not give magnitude at 50 Hz..

FFT Tutorial-LV2010 FPGA

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Any tutorial for FFT in FPGA for LV 2010??

LV2010-FPGA-FFT

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Can we determine the phase of a signal using FFT??. or is there any other method to determine the phase of 2 signals in FPGA?

Reduce TCP wait time after connection breaks

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Hi

 

I am running code on NI9651, based on RT Linux. (My application would like to connect to the server for prolonged intervals, and if it somehow gets disconnected, should be able to reconnect to the system as soon as possible.)

 

I try to connect to the system using TCP/IP, port 6123 which is working fine, even with multiple cilents at a time. Now when the server, (here 9651) resets all of a sudden, the connection breaks, without sending a formal close command to the client. Next time I run the code, I get error 60 at my TCP listen VI, which says that the port is in use, hence I cannot reconnect to system from my client. The server waits exactly for 60 seconds, after which I am able to reconnect to it from my client. 

 

From what I understand, if a formal close command is not sent and acknowledged, the server tries to reconnect to the old clients for 60 seconds before releasing the port again. For this reason, I added TCP_fin_timeout parameter = 10, TCP_tw_recycle = 1 and TCP_tw_reuse = 1 in the corresponding Linux file, at /etc/sysctl.conf. Even now, the server takes exactly 60 seconds to release the port. 

 

Is there any method by which I can reduce the TCP wait time in my Linux server side?

 

Thanks

Arya

 

 

NI 9401 counter/digital input/output

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Hello,

 

I am a beginner in national instrument product and labview. I bought a NI 9401 and a cDAQ 9174 chassis for my project. Sorry to ask this question but I am really confused about the counter and digital usage of NI 9401. It has 8 channel DIO 0 to 7. Does that means it has 8 counters as well? Can I wire 8 5V TTL signals into all the input terminal DIO 0 to 7?

 

I am looking forward to the replies. 

How to run a labview model on a VxWorks RTOS

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Hello

 

Currently I have been building a custom device model in order to run a labview controller model on VxWorks RTOS. 

I am using LabVIEW 2013sp1, VeriStand 2013SP1, and compactRIO 9024, and the controller model was written on discrete time system using Control and Simulation Loop. 

 

My questions are

1.  Is there no way but creating a custom device in order to run a labview controller model on a VxWorks RTOS? 

    ( In case of running an unsupported model on a VxWorks RTOS, custom device should be used.)

 if there is another way, could you please let me know how to do it?

 

2. Should I always put a labview controller model inside <custom device name> RT Driver VI.vi of custom device template? 
   If no, how should I load a labview controll model to use in veristand? or where should I place a labview controller model?

 

3. How can I synchronize the time of a labview controller model with real-time? 
    I am now using asynchronous execution mode of custom device, and tried to use timed loop in <custom device name> RT Driver VI.vi to synchronize with real timebut it didn't work because my labview controller model was built in Control and Simulation Loop. 

 

Any advices would be helpful. 

Thank you in advance.

 

Hongjun

Gain error with shunt calibration

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Hello,

 

I have a problem with shunt calibration of bridge based displacement transducers. The shunt calibration routine sets gain factors that give errors around 2% in the measured displacement. I have also found that the shunt calibration gain factors run out of bounds without a preceding offset null.

 

The hardware is a cDAQ-9188 with 9237 modules. The gauges have four wires, two input wires that I have connected to EX+ with jumper to RS+ and EX- with jumper to RS-/SC-, and two output wires that I have connected to AI+ with jumper to SC+ and AI-. LabVIEW is used with a VI shown in the attached figure.

 

Does anyone know why the shunt calibration behaves like that or what I do wrong?

 

/Emil

 


Sine wave - max/min

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Hi,

 

I have a question for you guys.

 

How do a generate a sine wave if I have two values, one is supposed to be the max value and the other the min.

Both these values comes in form of a byte array from a text file.

 

I can´t send negative values to the device therefore I want to set the two values so the sine wave is going from one to the other.

 

My problem is when I simulate a sine wave the amplitude is both negative and positive. My device can't handle that. 

 

How do I fix this?

 

Cheers /andechr

 

Sound Output fills up memory

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Hi,

 

I need to do a sound test in which pink noise is played for many hours. I generate the noise waveform with no problem, but when I add the SO blocks they slowly increase the memory usage until it is filled up to 3.7GB and the VI stops. Why is this happening? Is there an alternative way to send the output to the sound card?

 

Any suggerstion is appreciated!

Thanks

How to write TDMS file with two parameters ?

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Hello. Im using LabVIEW 2013 with myRIO 1900. I need to know how i can write a tdms file with two parameters. Ive converted my data into waveform using DDT and then wired it into the TDMS write. When i open the file all i get is the sensor readings. I need to know how i can show variation of my sensor input with time or input coming in from any other channel. 

 

Thanks in advance. 

Beating my foot with a hammer, or using PPLs - which is less painful?

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LV2013 SP1, LVRT 2013, Win7

 

I'm new to PPLs (Packed Project Libraries) and it looks like they might solve a couple of problems for me, but they seem to want to be contrary sometimes.

 

I've boiled it down to a simple case.  The BROKEN error has come and gone over the past week, I don't understand what brings it on or takes it away.  Today I moved the building of certain PPLs out of the main project and into a separate project, and here it is again.

 

Here is a 55 -sec JING to show the problem <http://www.screencast.com/t/4NvcjQmVeus>

 

0:00 I have a LVLIB called JENKINS HASH, I want to make a PPL out of it.  It contains five files (The "64" versions are not used, but similar to the "32" versions, which I DO use).

 

0:02 I open the HASH 32 PANEL.  It's marked as INLINE SUBROUTINE, but I've tried using it as normal, with no effect.  Note that IT IS NOT BROKEN.

 

0:04 the Block Diagram shows some arithmetic code, with 3 calsl to a single subVI, and a TYPEDEF (the "hash" outputs).

 

0:07 the SubVI has nothing but arithmetic code in it. No calls elsewhere.  It is also marked INLINE SUBROUTINE, but changing that has no effect.

 

0:13 the one TYPEDEF used is a simple U32, formatted a particular way.  It is also in the LVLIB.

 

0:21 - the BUILD SPEC for the PPL is shown.  The output is called JENKINS HASH.LVLIBP.

 

0:28 - the only thing in the SOURCE FILE is the single TOP LEVEL LIBRARY, Jenkins Hash.

(I'm using this project for other PPLs too, but they're not germane to this issue).

 

0:32 - BUILD the thing.  Takes about a second, and you see the new file appear where it's supposed to.

 

0:39 - Open the PPL (*.lvlibp) and you see the five files in it.

 

0:41 - Open the VI from the PPL and IT IS BROKEN ?  ? ?

 

WHY, you might ask.  Well, just click on the broken arrow and LV will tell you, right?

 

0:45 - Click on the arrow and it tells me "something is missing".

It's not smart enough to tell me WHAT,

 

If I wanted programming to be painful, I would move to Microsoft C++.

 

Any ideas?

 

 

 

 

shared variables

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Hello,
 
I have an application (LV2013) that uses shared variables on the network.
When I build the application and I install it on the PC where I have developped it, the variables are properly distributed and accessible over the network.
When I install this application on another PC (without Labview), the variable distribution service sends an error message and the variables are not running (pj err_Labview.png).
 
Do you have any idea on what I could forget to do?
Thank you.

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