Network buffers versus RT FIFO versus Implementation Details

Hello,

can anybody provide information on how the Shared Variable Engine (SVE) is implemented (threads, priority, etc.)?

Specifically, I'd like to formally understand the properties implemented by a combination of RT FIFO with network buffers.

The official NI white paper (http://www.ni.com/white-paper/4679/en/) doesn't explain the rationale of chaining up buffers (an RT FIFO is also a buffer). See Figure 14.  

Without additional explanation, I would need to know what the SVE really does.

Can anybody name an application where such a combination is needed, and where a single RT FIFO or single network buffer wouldn't make it?

Thanks!

Peter