I work for a company where we use CRIO 9041's for a product where we collect high speed data on FPGA, push that data to an FPGA queue and then read the data, average it with a moving window in the RT to be used for processing.
Code PIC is attached.
In the FPGA code, we write 9 readings one by one in the queue and then on the RT read side, we read them 9 elements at a time.
In the FIFO read, the RT completely stops reading the queue, and even the log VI doesnt log anything. We just see the elements remaining start going up to more that like 15000 elements and then the queue times out.
Seems like the RT totally stops reading from the quque. Almost like the RT dies.
Then when the fpga queue starts being read again, there is always one element in the queue remaining because of which our read of 9 sensors is shifted by one. So the code with the feedback loop was added as a temporary solution to shift our read of 9 elements when the elements remaining is non zero.
All of this is random as the system is idle.
